CHUBU UNIVERSITY
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ISHII Kiyoshi

Profile

Title Professor
Belong to Dept. of Electrical and Electronic Engineering
Dept. of Electronics and Information Engineering
Electrical and Electronic Engineering (graduate school)
Graduated Shinshu University, Graduate School of Engineering
Degree Dr. of Engineering, Shinshu University
Academic Institutional Membership IEEE, The Institude of Electronics Information and Communication Engineers, The Japan Society of Applied Physics
Field of Study Integrated Electronics
Research, Studies Design and Analysis of Integrated Circuits
Curriculum Specialized Advanced Electronic Circuits, Electric Circuits, Laws of Electrical Communication

Books Published, Translation

New Inter University Electric Circuits II (joint work), Ohmsha, 2010

Academic Papers, Critique

Recent progress in 40- to 100-Gbit/s-class optical communication ICs using InP-based HBT technologies, International Journal of High Speed Electronics and Systems, Vol.15, No.3, 2005

High-Bit-Rate Low-Power Decision Circuit Using InP-InGaAs HBT Technology, IEEE J. Solid-State Circuits, Vol.40, No. 7, 2005

90 Gbit/s 0.5 W decision circuit using InP/InGaAs double heterojunction bipolar transistors, IEE Electron. Lett., Vol.40, No.16, 2004

3.21 ps ECL gate using InP/InGaAs DHBT technology, IEE Electron. Lett., Vol.39, No.20, 2003

Over 40 Gbit/s 16:1 multiplexer IC using InP/InGaAs HBT, IEE Electron. Lett., Vol.39, No.12, 2003

4-bit Multiplexer/Demultiplexer Chip Set for 40-Gbit/s Optical Communication Systems, IEEE Transactions on Microwave Theory and Techniques, Vol.51, No.11, 2003

High-Input-Sensitivity, Low-Power 43 Gbit/s Decision Circuit using InP/InGaAs Double-heterojunction Bipolar Transistors, IEE Electron, Lett., Vol.38, No.12, 2002

Very-High-Speed Selector IC using InP/InGaAs Heterojunction Bipolar Transistors, IEE Electron. Lett., Vol.38, No.10, 2002

Low-power 1:16 DEMUX and One-Chip CDR With 1:4 DEMUX Using InP-InGaAs Heterojunction Bipolar Transistors, IEEE J. Solid-State Circuits, Vol.37, No.9, 2002

A Jitter Suppression Technique for a 2.48832-Gb/s Clock and Data Recovery Circuit, IEEE Transactions on Circuits and Systems II., Vol.49, No.4, 2002

A Jitter Suppression Technique for a Clock Multiplier, IEICE Trans. Electron., vol. E-83-C, No.4, 2000

Very-High-Speed Si Bipolar Static Frequency Dividers with New T-Type Flip-Flops, IEEE J. Solid-State Circuits, Vol.30, No.1, 1995

Maximum Operating Frequency in Si Bipolar Master-Slave Toggle Flip-Flop Circuit, IEEE J. Solid-State Circuits, Vol.29, No.7, 1994

High-Bit-Rate, High-Input-Sensitivity Decision Circuit Using Si Bipolar Technology, IEEE J. Solid-State Circuits, Vol.29, No.5, 1994

Sub-100-nm-Scale Patterning Using a Low-Energy Electron Beam, Jpn. J. Appl. Phys. 31(1992)L744.

Very-Low-Energy Electron Beam Lithography Using a Retarding Field, Jpn. J. Appl. Phys. 29(1990)2212.

The Interfacial Characteristics of MIS Structures Using Carbon Films as Insulator, The Transactions of The IECE of JAPAN, Vol. E69, No.4, 1986

Lectures, Symposium, Presentation

Circuit Technique for High-Speed MOSFET Voltage-Controlled Oscillators, The 32nd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2017), 2017 (Busan, Korea)

Analysis of Propagation-Delays in High-Speed Bipolar Gates, 2015 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2015), 2015 (Nusa Dua - Bali, Indonesia)

Circuit Technique for Improving Propagation Delay Times in CMOS Source-Coupled Logic Circuits, 2012 IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2012), 2012 (Tamsui, Taiwan)

Analysis of a High-Speed ECL Gate and Dynamic Flip-Flop with a Speed-Boost Circuit Technique using Transient Currents, The 26th International Technical Conference on Circuits/Systems, Computers and Communication (ITC-CSCC 2011), 2011 (Gyeongju, Korea)

Circuit Design for High-Speed T-Type Flip-Flops using SiGe HBTs, The 25th International Technical Conference on Circuits/Systems, Computers and Communication (ITC-CSCC 2010), 2010 (Pattaya, Thailand)

Novel Circuit Technique for High-speed ECL Gates, IEEE NEWCAS-TAISA'09, 2009 (Toulouse, France)

Very-High-Speed InP/InGaAs HBT Multiplexer ICs for Optical Communication Systems, ISPACS 2006, 2006 (Tottori, Japan)

High-bit-rate low-power decision circuit using InP/InGaAs HBT technology, IEEE ESSCIRC 2004, 2004 (Leuven, Belgium)

4-bit Multiplexer/Demultiplexer Chip Set for 40-Gbit/s Optical Communication Systems. 2003 IEEE Radio Frequency Integrated Circuits Symposium, 2003 (Philadelphia, USA)

1-W 1:16 DEMUX and One-Chip CDR With 1:4 DEMUX for 10 Gbit/s Optical Communication Systems, IEEE GaAs IC Symposium, 2001 (Baltimore, USA)

A Jitter Suppression Technique for a 2.48832-Gb/s Clock and Data Recovery Circuit, IEEE ISCAS 2000, 2000 (Geneva, Switzerland)

Circuit design for a 15-Gb/s Si bipolar decision circuit, IEEE 1992 BCTM, 1992 (Minneapolis, USA)

Very-Low-Energy Electron Beam Lithography Using a Retarding Field, 1990 3rd MicroProcess Conference, 1990 (Chiba, Japan)

Others

Visiting Professor of The University of New England, AUSTRALIA (2007)

IEEE Senior Member

IEICE Senior Member

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